OCP currently lists HBF as a semi-private workstream
OCP's public directory lists High Bandwidth Flash among its semi-private workstreams rather than in the main public project directory.
Catalog / 31 public records
Search the first indexed corpus of public HBF material. Vendor announcements, standards pages, peer-reviewed papers, preprints, and adjacent work remain visibly distinct.
OCP's public directory lists High Bandwidth Flash among its semi-private workstreams rather than in the main public project directory.
The public ONFI 6.0 specification defines NAND device interfaces and operating modes, including high-speed signaling used below system-level memory products.
NVIDIA's documentation explains direct data movement between storage and GPU memory with reduced CPU bounce buffering.
The paper explores capacity-oriented HBF uses in LLM serving, including model residency, expert replication, and multi-model deployment.
The study argues that HBF performs poorly as a drop-in SSD replacement for transient KV-cache traffic, while identifying selective, more read-oriented uses where it can remain valuable.
The companies announced an initial OCP HBF specification covering stack capacities up to 512 GB, three bandwidth grades, a UCIe host link, packaging and reliability, and software I/O guidance.
A hardware-managed heterogeneous memory proposal that studies how data can move between HBM and high-bandwidth flash during LLM inference.
A full-stack proposal for integrating high-bandwidth flash into AI systems, spanning media behavior, data movement, and model execution.
TileLens explores data layouts intended to reduce the mismatch between accelerator tensor access and flash's comparatively large transfer granularity.
The paper compares HBF-like flash with on-package LPDDR and argues that writability and KV-cache behavior can favor DRAM-based alternatives.
The paper examines the performance and lifetime consequences of placing write-intensive transformer KV caches in HBF.
A system proposal for pooling HBM and HBF behind a custom logic die to support terabyte-scale inference memory footprints.
The authors evaluate where HBF's density can help modern LLM serving and identify the architectural and software challenges that follow from NAND behavior.
SK hynix discussed AIN-B, a vertically stacked NAND architecture with a logic base die and high-bandwidth interface for AI workloads.
An accessible technical overview of HBF's proposed architecture, motivation, and place in next-generation AI systems.
A design-space exploration framework for AI inference systems that includes HBF among possible capacity, bandwidth, and cost tradeoffs.
Kioxia announced an SSD family designed for NVIDIA's Storage-Next architecture and high-IOPS, direct data paths into accelerated systems.
HAVEN proposes using HBF as a high-capacity tier for approximate nearest-neighbor search, moving beyond the dominant LLM-weight use case.
The companies announced the start of an Open Compute Project workstream to define a common HBF architecture and interface.
A survey and research agenda for inference hardware that situates emerging memory tiers, including HBF, inside the wider model-serving bottleneck.
The paper evaluates a heterogeneous HBM-HBF design for serving large language models under memory-capacity and cost constraints.
An engineering overview of using UCIe to connect logic-base-die memory stacks, including HBF-like flash configurations, to AI and HPC systems.
A package-level study of a hybrid HBM-HBF memory architecture using glass interconnect technology for large-model inference.
SK hynix described HBF as the bandwidth-oriented branch of its AI-NAND strategy and discussed vertically stacked NAND for AI systems.
Kioxia and partners reported a PCIe 6.0-connected flash module prototype delivering 5 TB capacity and 64 GB/s aggregate bandwidth at under 40 W.
A company-authored explanation of why model capacity and data movement motivate a new tier between HBM and conventional storage.
The companies announced an agreement to define interoperable HBF specifications and build a broader ecosystem around high-capacity, high-bandwidth flash memory.
UCIe 3.0 adds 48 and 64 GT/s operation plus manageability and system-in-package improvements for interoperable chiplets.
Sandisk announced a group of academic and industry advisers intended to guide HBF architecture, software, standards, and ecosystem strategy.
A two-page overview of the HBF concept, its proposed system role, projected stack organization, and comparison with conventional high-bandwidth memory.
Sandisk's investor presentation introduced HBF as a vertically integrated, capacity-oriented memory tier for AI inference and set out the earliest public product roadmap located by this project.