StandardsCore HBF
OCP currently lists HBF as a semi-private workstream
OCP's public directory lists High Bandwidth Flash among its semi-private workstreams rather than in the main public project directory.
Public record / checked 16 Aug 2026
HBF standards tracker
This page separates a released announcement from a retrievable specification, and a paper specification from measured production hardware.
Public fact matrix / 01
Current public facts
FieldPublic valueStatusEvidence
Values above come from company and standards-process announcements. They are not independent silicon measurements.
Known
Scope covered by the announced specification
The August 2026 announcement says the first package covers system and electrical requirements, host interface, packaging and reliability, plus software I/O guidance.
Still unknown publicly
Implementation details not yet available
A stable specification-document URL, compliance process, independent benchmarks, production device data sheets, pricing, and general availability remain unlocated or unannounced.
Standards source trail / 02
Primary standards records
StandardsAdjacent technology
ONFI 6.0 defines the underlying NAND interface layer
The public ONFI 6.0 specification defines NAND device interfaces and operating modes, including high-speed signaling used below system-level memory products.
StandardsCore HBF
The first HBF specification package is announced
The companies announced an initial OCP HBF specification covering stack capacities up to 512 GB, three bandwidth grades, a UCIe host link, packaging and reliability, and software I/O guidance.
StandardsCore HBF
The OCP HBF workstream formally begins
The companies announced the start of an Open Compute Project workstream to define a common HBF architecture and interface.
StandardsCore HBF
Sandisk and SK hynix align on HBF standardization
The companies announced an agreement to define interoperable HBF specifications and build a broader ecosystem around high-capacity, high-bandwidth flash memory.
StandardsAdjacent technology
UCIe 3.0 doubles die-to-die data rates
UCIe 3.0 adds 48 and 64 GT/s operation plus manageability and system-in-package improvements for interoperable chiplets.